1. Field of the Invention
The present invention relates to a test apparatus and a test method. More particularly, the present invention relates to a test apparatus and a test method for adjusting a delay amount of a clock signal by reason of a test.
2. Related Art
Recently, a semiconductor memory capable of being fast accessed has adopted source synchronous clocking. Such a semiconductor memory personally generates a clock signal synchronized with a data signal in addition to the data signal. An outside device can read the data signal in synchronization with this clock signal to access the semiconductor memory at high speed and effectively.
A conventional test apparatus adjusts a reference clock signal for test so as to synchronize the reference clock signal with the clock signal acquired from the semiconductor memory in order to test such a semiconductor memory. Then, the test apparatus tests whether the data signal can be read based on this adjusted reference clock signal. The test apparatus generates an artificial delay for the reference clock signal by means of a strobe signal, and also tests whether data can be read if the delay is within a reference range.
The data signal generated from the semiconductor memory may have a jitter. When the data signal has a jitter, the clock signal generated from the semiconductor memory may have a similar jitter in many cases. On the other hand, the reference clock signal in the conventional test apparatus is not affected by the jitter produced in the clock signal once the clock signal has been adjusted. For this reason, since a phase difference by the generation of jitter occurs between the reference clock signal and the data signal, this may cause the decrease of the precision of test.